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NXP Semiconductors /MIMXRT1021 /LPI2C1 /MCR

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Interpret as MCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MEN_0)MEN 0 (RST_0)RST 0 (DOZEN_0)DOZEN 0 (DBGEN_0)DBGEN 0 (RTF_0)RTF 0 (RRF_0)RRF

RTF=RTF_0, RRF=RRF_0, DOZEN=DOZEN_0, MEN=MEN_0, DBGEN=DBGEN_0, RST=RST_0

Description

Master Control Register

Fields

MEN

Master Enable

0 (MEN_0): Master logic is disabled

1 (MEN_1): Master logic is enabled
RST

Software Reset

0 (RST_0): Master logic is not reset

1 (RST_1): Master logic is reset
DOZEN

Doze mode enable

0 (DOZEN_0): Master is enabled in Doze mode

1 (DOZEN_1): Master is disabled in Doze mode
DBGEN

Debug Enable

0 (DBGEN_0): Master is disabled in debug mode

1 (DBGEN_1): Master is enabled in debug mode
RTF

Reset Transmit FIFO

0 (RTF_0): No effect

1 (RTF_1): Transmit FIFO is reset
RRF

Reset Receive FIFO

0 (RRF_0): No effect

1 (RRF_1): Receive FIFO is reset

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data